1. Field of the Invention
The present invention relates to a method of forming a doped region on a silicon on insulator (SOI) layer, and more particularly, to a method of forming a super steep retrograde (SSR) distribution of the doping concentration in a doped region.
2. Description of the Prior Art
SOI layers are a new technology for the isolation of CMOS devices. Its principle feature is the formation of a dielectric layer on the surface of a substrate, and then the formation of a silicon layer on the dielectric layer. Hence, the silicon layer used to manufacture a CMOS device is separated from the substrate by a dielectric layer, and latch-up, which often occurs in CMOS transistors, is prevented.
Please refer to FIG. 1 to FIG. 5. FIG. 1 is a cross-sectional diagram of an SOI layer structure of the prior art. A dielectric layer 12 and a silicon layer 14 are formed in order on the substrate 10 to form an SOI layer. FIG. 2 to FIG. 5 are cross-sectional diagrams of a method for forming a doped region on an SOI layer of the prior art. The method of the prior art involves first forming a shallow trench isolation structure 16 in a predetermined position of the silicon layer 14. The shallow trench 16 passes through to the dielectric layer 12. Then, as shown in FIG. 3, a dielectric layer 18 or a photoresist layer (not shown) is formed on the predetermined N-well region of the silicon layer 14, and serves as a hard mask. An ion implant process 20 is performed in the predetermined P-well region of the silicon layer 14 to form a P-well 22 doped region.
Then, as shown in FIG. 4, the dielectric layer 18 is removed and a dielectric layer 24 or a photoresist layer (not shown) is formed on the P-well 22 of the silicon layer 14 to serve as a hard mask. An ion implant process 26 is performed in the predetermined N-well region to form an N-well 28 doped region. Finally, as shown in FIG. 5, the dielectric layer 24 is removed and the process of manufacturing doped regions on an SOI layer is finished.
Please refer to FIG. 6. FIG. 6 is a cross-sectional diagram of a PMOS transistor formed in the N-well after forming the doped regions on an SOI layer by the prior art method. Please refer to FIG. 7 and FIG. 8. FIG. 7 is a diagram depicting the doping distribution in the PMOS transistor along the line 2-2' of FIG. 6. FIG. 8 is a diagram depicting the doping distribution in the PMOS transistor along the line 3-3' of FIG. 6. The P-well 22 and the N-well 28 on the SOI layer are used to form NMOS and PMOS transistors to structure each step of the very large scale integration (VLSI) process. As shown in FIG. 7, the diagram illustrates the doping concentration versus depth in the PMOS transistor on the SOI layer formed by the prior art method along the line 2-2'. Experimental results have shown that the channel doping distribution curve 27 of the MOS transistor is relatively uniform and the doping concentration is relatively high on the wafer surface near the gate 34.
This high, uniform doping distribution results in reduced mobility of electrons and holes, and may cause short channel effects (SCE). As shown in the doping distribution curve 29 of FIG. 8, the doping concentration is typically large in both the source 40 and the drain 42. Because the doping concentration at the interface of the source 40 and the N-well 28, or the drain 42 and the N-well 28, is much lower than other source or drain regions, a higher junction capacitance (Cj) may appear at the interface, affecting the electrical performance of the MOS transistor.